The invention relates to a memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”). Further, the invention relates to a method for fabricating said memory device, in particular a Phase Change Random Access Memory device.
In so-called resistive or resistively switching memory devices an active or switching active material can be switched by an appropriate switching process into a first, conducting state and a second, non or less conducting state wherein the conducting state corresponds to a logic “one” and the less conducting state can be assigned a logic “zero”, or vice versa. A first kind of these memory devices is so-called Phase Change Random Access Memory, hereinafter called PCRAM. Furthermore so-called Conductive Bridge Random Access Memory (“CBRAM”) and other types of resistively switching memory types are known.
In particular for PCRAM a chalcogenide or chalcogenide compound can be used as a “switching active” material, e.g. a Ge—Sb—Te (GST) or an AG-In—Sb—Te compound. This “switching active”, e.g. the chalcogenide material, can be switched between an amorphous and a crystalline state, wherein the amorphous state is the relatively weakly conducting state, which accordingly can be assigned a logic zero, and the crystalline state, i.e. a relatively strongly conductive state, accordingly can be assigned a logic one. In the following this material will be referred to as the switching active material.
To achieve a change from the amorphous, i.e. a relatively weakly conductive state of the switching active material, to a crystalline, i.e. a relatively strongly conductive state, the material has to be heated. For this purpose a heating current pulse is sent through material, which heats the switching active material beyond its crystallization temperature thus lowering its resistance. In this way the value of a memory cell can be set to a first logic state, i.e. a logic one.
Vice versa, the switching material can be heated by applying a relatively high current to the cell which causes the switching active material to melt and by subsequently “quench cooling” the material can brought into an amorphous, i.e. relatively weakly conductive state, which may be assigned the second logic state, that is to reset the first logic state.
Typically, the heating current pulses are provided via respective source lines and bit lines, wherein the current pulse is controlled by selection transistor, with which a memory cell can be selected from an array of memory cells arranged in a memory device, which typically is an integrated circuit (IC). The state of said selection transistor typically is controlled by a word line, which is coupled to the gate of the selection transistor. The drain of the selection transistor is coupled to the switching active material, such that a current flowing through the selection transistor is conducted through the switching active material, thus the heating current pulse is controlled by the transistor.
An ever-challenging problem is to reduce the size of such a memory cell. One approach known from prior art is to improve the thermal isolation of a cell to accelerate the process of heating. Furthermore attempts have been made to limit the size of the current path in order to concentrate the current onto a small area and thus to achieve a high current density within the switching active material.
To further reduce the size of such a memory cell and to improve the behavior there is a need for the present invention.